With the trend to continue to miniaturize semiconductor integrated circuits to achieve submicron feature sizes, packing density becomes important. The number of components that can be manufactured on a chip can be increased through the decrease of the horizontal dimensions of the various components. However, horizontal dimensions cannot be scaled down without a corresponding decrease in the components' vertical dimensions.
Several approaches to scale down the size of transistors have been proposed in the prior art. One approach to scale down the size of a transistor is to decrease all dimensions by the same factor. When all dimensions are decreased, including the depth of the source/drain regions, a decrease in the surface concentration of dopants in the source/drain regions occurs. This approach may cause problems in transistor fabrication, more specifically in the electrical characteristics of the source/drain regions. Such a decrease in dopant concentration along with a shallower junction of the source/drain depth causes an unwanted increase in the resistivity of the source/drain regions. Another approach is to maintain the junction depth and original dopant concentration while decreasing the horizontal dimensions. This method may result, however, in unacceptable short channels. An additional approach is to increase the dopant concentration while decreasing the junction depth of the source/drain regions. This method may provide for acceptable resistivities of the source/drain regions. However, the dopant gradient is higher in a shallower junction generating a large electrical field. Such an effect is responsible for the "hot electron" problem which degrades the transistor and leads to reliability problems.
A well known solution to the transistor scaling problem involves forming lightly doped drain (LDD) regions. The LDD structures are formed by using two implantation steps when forming the source/drain regions. After the gate electrodes are formed, a first implant with an N-type dopant is made to form a lightly doped, very shallow source and drain. Sidewall oxide spacers are formed along the sides of the gate electrode. A second implant is then made with a large dose of dopant into the source/drain regions. This second implant is made to reduce the resistivity in these regions. The heavier implant is masked by the gate and the sidewall oxide spacers. Thus, the source/drain regions adjacent to the gate are lightly doped and the regions adjacent to the sidewall oxide spacers are heavily doped.
Problems have occurred in forming the LDD structures using the sidewall oxide spacers. Negative charges may build up on top of the LDD structure not directly under the gate electrode. As reported in "A Novel Submicron LDD Transistor With Inverse-T Gate Structure'" by Tiao-yuan Huang et al, published in 1986 in the IEDM, pages 742-745, the LDD region may become depleted by the trapped negative charges. The source/drain resistance may thus increase causing a faster degradation rate of the transistor.
Tiao-yuan Huang et al proposed an inverse-T LDD transistor to eliminate the oxide sidewall "spacer induced degradation." At gate formation, the polysilicon gate is only partially etched instead of being etched down to the gate oxide layer as in the conventional LDD transistor. A thin polysilicon layer is left on the oxide layer. The first implant is made to form the N.sup.- LDD regions. Sidewall oxide spacers are formed along the sidewalls of the polysilicon gate and on top of the thin layer of polysilicon adjacent to the gate. The remaining thin layer of polysilicon is then removed and the second heavy implant is made to form the source/drain regions using the spacers as a mask. The source/drain regions thus become self-aligned to the gate having an inverse-T shape.
While this process of forming LDD regions increases device reliability and eliminates the "spacer-induced degradations," this process has inherent manufacturing limitations. The method of etching partially through the polysilicon layer is difficult to control to obtain both a desired structure and thickness. It would therefore be desirable to provide a method which produces a reliable inverse T transistor having the desired structure and thickness. It would also be desirable for such a technique to reduce the channel electric field and eliminate the "spacer-induced degradation." It would further be desirable for such technique to be easily adapted for use with standard integrated circuit fabrication process flows without increasing the complexity of the process.